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低功耗高性能電流式感測放大器設計

為了解決RX300 Mobile01的問題，作者梁文顏 這樣論述：

Table of ContentsRecommendation Letters from Thesis AdvisorsThesis/Dissertation Oral Defense Committee CertificationPreface iiiAbstract ivTable of Contents vList of Figures viiList of Tables xiChapter 1 Introduction 11.1 Memory and Processors 21.2 Sense Amplifiers 31.3 Technology Trends 41.4 Circui

t Trends 51.5 Other Trends 61.6 SRAM Trends 71.7 Associated Challenges 9Chapter 2 A Circuits Survey 102.1 The Two Broad Classes 102.2 Voltage Sensing 122.3 Current Sensing 162.4 Others 20Chapter 3 Development of a Three-Transistor I–V Converter 223.1 Low Drop-Out Voltage Regulator as a I–V Converter

233.2 I–V Converter as a Current Sense Amplifier 253.3 Simplifying the I–V Converter 253.4 Proof of Concept 273.5 Quest for a Better Error Amplifier 293.6 Revisiting the Proof of Concept 31Chapter 4 Implementation of a Current Sense Amplifier 344.1 Sense Amplifier Shut-Down 344.2 Static Power Reduc

tion 364.3 Pulsed Word-Line Operation 374.4 Bit-Line Capacitance—Effect on Delay 394.5 Bias Variation 414.6 Relevant Concerns 43Chapter 5 Conclusion 445.1 Simulation Results 445.2 Considerations for Long Bit-Lines 465.3 Measurements 475.4 Derivative Circuits 495.5 Derivative Use 525.6 Summary 555.7

Final Thoughts 55References 56Appendices 83List of FiguresFigure 1.1 Die micrograph from [Singh et al., 2018] 2Figure 1.2 Layout from [Takemoto et al., 2020] 2Figure 1.3 Package from [Poulton et al., 2019] 4Figure 1.4 Wearable for happiness index from [Yano et al., 2015] 6Figure 1.5 Test chip from [

Song et al., 2017] 7Figure 2.1 Left–right: nMOS common-source, -gate and -drain amplifier configurations 10Figure 2.2 Left–right: pMOS common-drain, -gate and -source amplifier configurations 11Figure 2.3 Bi-stable constructed of two inverters 11Figure 2.4 Regenerative latch transient simulation out

put 11Figure 2.5 nMOS differential pair 12Figure 2.6 nMOS–input pair differential amplifier 13Figure 2.7 Clocked latch with isolation 14Figure 2.8 Current-controlled latch 15Figure 2.9 Left–right: Resistor and nMOS approximates 16Figure 2.10 Left–right: Resistor and pMOS approximates 16Figure 2.11 n

-p-n common-base amplifier 17Figure 2.12 Partial schematic from [Yeo and Rofail, 1995] 17Figure 2.13 Left–right: nMOS and pMOS current mirrors 18Figure 2.14 Current sense amplifier from [Ishibashi et al., 1995] 18Figure 2.15 Current sense amplifier from [Seno et al., 1993] 19Figure 2.16 Current conv

eyor from [Seevinck et al., 1991] 19Figure 2.17 pMOS-neutralised nMOS differential pair 20Figure 2.18 Λ-type negative resistance from [Wu and Lai, 1979] 21Figure 2.19 I D -V D characteristic of the Λ-type negative resistance 21Figure 3.1 Three-transistor I–V converter 22Figure 3.2 Simplified low dro

p-out voltage regulator 23Figure 3.3 Low drop-out voltage regulator configured as a I–V converter 24Figure 3.4 Low drop-out voltage regulator as a current sense amplifier 25Figure 3.5 Reference-free I–V converter 26Figure 3.6 Logic inverters as positive-gain amplifier 26Figure 3.7 Proof of concept d

esign 27Figure 3.8 Proof of concept design transient simulation output 28Figure 3.9 Typical and unintended input(s) of the logic inverter 29Figure 3.10 Normalised absolute gain plot for each inverter input 30Figure 3.11 Connections made for the absolute gain plot 30Figure 3.12 Bias generator for the

absolute gain plot 31Figure 3.13 Error amplifier replacement in the proof of concept design 31Figure 3.14 Three-transistor I–V converter 32Figure 3.15 Corresponding bias generator of Figure 3.14 32Figure 3.16 Simulation circuit for verifying the improved error amplifier 33Figure 3.17 Demonstration

of the three-transistor I–V converter as a current sense amplifier 33Figure 4.1 Actions to achieve desired node characteristics during shut-down 34Figure 4.2 Figure 3.14 modified for shut-down 35Figure 4.3 Corresponding bias generator of Figure 4.2 35Figure 4.4 Shared use of bias generator 36Figure

4.5 Pseudo-differential version of Figure 4.4 37Figure 4.6 Pseudo-differential configuration of Figure 3.14 37Figure 4.7 Pulsed read of a ZERO 38Figure 4.8 Pulsed read of a ONE 38Figure 4.9 Differential development across dynamic bit-lines and csa outputs 39Figure 4.10 Delay behaviour with capacitiv

e bit-line loading 40Figure 4.11 Normalised csa bias current variation with supply voltage 41Figure 4.12 Normalised csa bias current variation with temperature 42Figure 4.13 Mismatch view of Figure 3.14 43Figure 5.1 Test set-up (external trigger connection not drawn) 47Figure 5.2 Oscillogram demonst

rating circuit functionality at VDD = 2.55V 47Figure 5.3 Test set-up photograph 48Figure 5.4 Left–right: Three-transistor I–V converter and its complement 49Figure 5.5 Transfer characteristics of the circuits in Figure 5.4 49Figure 5.6 Four-transistor I–V converter 50Figure 5.7 Corresponding bias ge

nerator of Figure 5.6 50Figure 5.8 Impact of sizing on AC performance 51Figure 5.9 Left–right: V SS -, V DD -referenced and floating optical receiver front ends 52Figure 5.10 Transfer characteristic of floating I–V converter 53Figure 5.11 High output resistance eases filter realisation 53Figure 5.12

Three-transistor I–V converter operating as an open-drain receiver 54Figure A.1 inv symbol 84Figure A.2 Alternate inv symbol 84Figure A.3 inv transistor-level schematic 84Figure A.4 inv4 symbol 85Figure A.5 inv4 transistor-level schematic 85Figure A.6 inv16 symbol 86Figure A.7 inv16 transistor-leve

l schematic 86Figure A.8 nand2 symbol 87Figure A.9 nand2 transistor-level schematic 87Figure A.10 nand2b symbol 88Figure A.11 nand2b gate-level schematic 88Figure A.12 nor2 symbol 89Figure A.13 nor2 transistor-level schematic 89Figure A.14 nor2b symbol 90Figure A.15 nor2b gate-level schematic 90Figu

re A.16 or2 symbol 91Figure A.17 or2 gate-level schematic 91Figure A.18 tinv symbol 92Figure A.19 tinv transistor-level schematic 92Figure A.20 dlat symbol 93Figure A.21 dlat gate-level schematic 93Figure A.22 dlatr symbol 94Figure A.23 dlatr gate-level schematic 94Figure A.24 dlats symbol 95Figure

A.25 dlats gate-level schematic 95Figure A.26 tie0 symbol 96Figure A.27 tie0 transistor-level schematic 96Figure A.28 tie1 symbol 97Figure A.29 tie1 transistor-level schematic 97Figure B.1 bit0 symbol 99Figure B.2 bit0 transistor-level schematic 99Figure B.3 bit1 symbol 100Figure B.4 bit1 transistor

-level schematic 100Figure B.5 blrc symbol 101Figure B.6 blrc cell-level schematic 101Figure B.7 pre symbol 102Figure B.8 pre transistor-level schematic 102Figure B.9 rblrc symbol 103Figure B.10 rblrc cell-level schematic 103Figure B.11 wr symbol 104Figure B.12 wr transistor-level schematic 105Figur

e B.13 anand2 symbol 106Figure B.14 Alternate anand2 symbol 106Figure B.15 anand2 transistor-level schematic 107Figure B.16 ckgen symbol 108Figure B.17 ckgen gate-level schematic 108Figure B.18 peri symbol 109Figure B.19 peri cell-level schematic 110Figure B.20 csa symbol 111Figure B.21 csa transist

or-level schematic 111Figure B.22 kobl symbol 112Figure B.23 Alternate kobl symbol 112Figure B.24 kobl transistor-level schematic 113Figure B.25 kobs symbol 114Figure B.26 kobs transistor-level schematic 114Figure C.1 sram1 symbol 116Figure C.2 sram1 block-level schematic 117Figure C.3 sram2 symbol

118Figure C.4 sram2 block-level schematic 119Figure C.5 sram3 symbol 120Figure C.6 sram3 block-level schematic 121Figure D.1 ainvl symbol 123Figure D.2 ainvl transistor-level schematic 123Figure D.3 ainvs symbol 124Figure D.4 Alternate ainvs symbol 124Figure D.5 ainvs transistor-level schematic 124F

igure D.6 cut symbol 125Figure D.7 cut cell-level schematic 126Figure D.8 inAmp symbol 127Figure D.9 inAmp cell-level schematic 127Figure D.10 CD4007 symbol 128Figure D.11 CD4007 transistor-level schematic 128Figure D.12 LF356 symbol 129Figure D.13 LF356 cell-level schematic 129Figure D.14 TL431 sym

bol 130Figure D.15 TL431 cell-level schematic 130Figure D.16 tialp symbol 131Figure D.17 tialp transistor-level schematic 131Figure D.18 tiasd symbol 132Figure D.19 tiasd transistor-level schematic 132Figure D.20 tiasn symbol 133Figure D.21 tiasn transistor-level schematic 133Figure D.22 tiasp symbo

l 134Figure D.23 tiasp transistor-level schematic 134Figure E.1 nfet and equivalent nMOS symbol 135Figure E.2 pfet and equivalent pMOS symbol 136Figure E.3 Circuit for estimating per-bit junction capacitance 137Figure E.4 Simulation output for estimating per-bit junction capacitance 138Figure E.5 Ci

rcuit for estimating per-bit bit-line leakage current 138Figure E.6 ID-VD characteristics 139Figure E.7 ID-VG characteristics 140Figure E.8 anand2 transistor-level schematic 141Figure E.9 Test board functional blocks 144Figure E.10 Test board block-level schematic 145Figure E.11 Signal source connec

ted to abbreviated input network 148Figure E.12 General form of a typical instrumentation amplifier 150Figure E.13 Inverting integrator section of test board 154List of TablesTable 1.1 Semiconductor memory hierarchy 1Table 5.1 Column height h = 512b 44Table 5.2 Column height h = 1Kb 44Table 5.3 Colu

mn height h = 2Kb 44Table 5.4 Summarised measurement results 48Table A.1 List of standard cells 83Table A.2 inv truth table 84Table A.3 inv4 truth table 85Table A.4 inv16 truth table 86Table A.5 nand2 truth table 87Table A.6 nand2b truth table 88Table A.7 nor2 truth table 89Table A.8 nor2b truth tab

le 90Table A.9 or2 truth table 91Table A.10 tinv truth table 92Table A.11 dlat truth table 93Table A.12 dlatr truth table 94Table A.13 dlats truth table 95Table A.14 tie0 truth table 96Table A.15 tie1 truth table 97Table B.1 List of custom cells 98Table B.2 pre truth table 102Table B.3 wr truth tabl

e 104Table C.1 SRAM cells and read path configurations 115Table D.1 List of other cells 122Table E.1 Transistor performance 140Table E.2 Primary bill of materials 146Table E.3 Additional hardware 147Table E.4 List of instruments 155Table F.1 List of abbreviations 158Table F.2 List of symbols 159Tabl

e F.3 List of AC quantities 160Table F.4 List of DC quantities 161Table F.5 List of partial-swing signals 162Table F.6 List of rail–rail signals 162Table F.7 List of instance names 163

用於便攜式電子設備電源充電器的綠色能源無線電源充電器墊

為了解決RX300 Mobile01的問題，作者孔考儒 這樣論述：

便攜式無線電源充電器設備在市場中迅速成長，該設備有可能成為便攜式電子設備的標準電源充電器。在這項工作中設計並實現了一種創新的便攜式無線電源充電器，該充電器不僅可以增強用戶體驗，且更加環保。該設備設計為以可再生能源為主要電源運行。開發的充電器系統為下一代電源充電器系統提供了簡單性，增強的用戶便利性和體驗，用戶和環境友好，低成本且可靠的特點。從能源的角度來看，可再生能源的使用促進了乾淨和更高效的能源，與化石能源相比，這對環境沒有負面影響。此外，開發的系統還具有一些優勢，例如最少或沒有外部充電配件，可同時用於多個設備，並降低了電擊危險。基於電磁感應技術應用無線電力傳輸（WPT）系統，以便以110

kHz的工作頻率傳播電磁能量。它符合無線電源聯盟（WPC）標準。圓形扁平螺旋空心線圈的幾何形狀和發射器陣列線圈用於提高功率傳輸效率，並允許多個設備同時以其自由位置和方向充電。引入了數值計算和分析方法來評估單線圈和陣列線圈設計中的線圈幾何形狀。有些已經實現了無線電源充電器墊原型，以演示創新的便攜式設備充電器應用，例如緊湊型充電器墊，混合動力銀行充電器墊，耳機充電器墊以及自由位置和方向充電器墊。具有低輸入電壓功能，開發的無線充電器原型可以使用由可再生能源（例如太陽能電池和燃料電池）提供的電源運作。實驗測試和驗證顯示，開發的系統在Tx和Rx線圈之間的5-0 mm距離處的傳輸效率在60-70％的範圍內

，功率傳輸在4-5 W的範圍內。4單元質子交換陰極側採用開放式薄膜燃料電池（PEMFC）平面模塊，已在實驗室測試台上使用，可提供低壓和高電流特性，從而提供動力。燃料電池可在2.03 V時提供4 W的功率，電流高達2000 mA，原型可透過無線電力接收器設備在4.8 V時提供高達2.89 W的功率向負載傳輸功率，在4.8 V時為600W。對於原型目的，其輸出功率足以為手機的內置電池充電。使用手機作為目標設備的充電測試顯示，該原型能夠在3.3分鐘內將內置電池的容量增加約1％，並消耗約1200毫升的氫氣。手機電池容量為3.8 V，5.7 Wh。該充電測試證明了無線傳輸綠色能源的可行性。功能測試也證實

出，該原型具有更靈活的充電對準容差，更寬的發射範圍以及與其他符合WPC標準的設備的互操作性。