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考慮政府給定碳排放限制下兩階層綠色產品鏈之分權式決策

為了解決integratedcircuit中文的問題，作者嚴婕俞 這樣論述：

大眾消費者越來越重視碳排放議題，綠色產品(Green product)市場也隨著環保議題快速增長，許多企業為擴大市佔率而積極開發符合環保規範之綠色產品。然而，大部分綠色產品僅著重於產品本身之設計或產品之原料環保性與可回收性，而忽略產品在生產供應鏈相關方面產生之碳排放。為解決此問題，本研究提出一個模型並利用動態規劃(Dynamic Programming, DP)求解。此模型中包含兩名決策者，先行者(Leader)為上游設計商；追隨者(Follower)為下游製造商。為計算產品相關供應鏈產生之碳排放量，本研究採用生命週期評估(Life-cycle assessment，簡稱LCA)衡量產品生產

鏈活動中直接或間接產生之碳排放。模型中，上游設計商提出一個減碳回饋機制，減碳回饋即為每公斤碳排放減少，下游製造商可以得到之獎勵費用；下游製造商會依據上游設計商所提供的產品設計，依據不同的減碳回饋值決定其產品之生產供應鏈。透過減碳回饋機制，下游製造商在決定其產品供應鏈決策時，會將碳排放納入考慮，而選擇較環保的產品供應商，此模型也可以協助上游設計商在同質性綠色產品中挑選出符合環境規範之產品設計。本研究提供了一個決策系統給上游設計商和下游製造商，上游設計商能透過此決策系統權衡碳排放與成本的關係後決定其決策，此決策為產品設計及減碳回饋值，下游製造商能找出與此決策相對應的最佳供應鏈配置。換言之，此決策系

統能提供上游設計商找出符合碳排放限制下的多組最佳解與其對應的碳排放與成本，上游設計商可權衡碳排放與成本後選擇其較喜歡的決策，也能協助下游製造商針對不同產品設計及減碳回饋值下選擇其最佳的供應鏈決策。最後，根據檯燈的真實數據為案例分析，針對分權式模型之結果，提出兩名決策者在供應鏈決策的建議。

應用於超寬頻收發器之射頻積體電路研製

為了解決integratedcircuit中文的問題，作者葉金益 這樣論述：

Table of Contents指導教授推薦書口試委員審定書誌謝...........................................................iii中文摘要.........................................................ivAbstract.....................................................viiTable of Contents..............................................xFigure Captio

ns................................................xivTable Captions...............................................xxiChapter 1 Introduction..........................................11-1 Background and Motivation...................................11.2 Research Goals...................................

...........71-3 Thesis Organization.........................................8Chapter 2 Design of RF CMOS Amplifier for UWB Applications.....102-1Introduction................................................102-2 Compact Green Design Structure of Distributed Amplifier forUWB Wireless Receivers........

.................................112-2-1 Principles...............................................122-2-1-1 Shunt Feedback LNAs....................................132-2-1-2 Common-gate LNAs.......................................142-2-1-3 Cascoded Common-source LNAs............................152-2-1

-4 Distributed LNAs.......................................152-2-2 Circuit Design...........................................162-2-3 Measuring................................................282-2-3-1 Measurement Setup Structure............................282-2-3-2 IC-CAP Features......................

..................312-2-3-3 Measurement Results....................................342-2-4 Discussion...............................................372-3 3.1-10.6GHz UWB Low-Power CMOS Power Amplifier.............412-3-1 Principles of Current-reused Technology..................422-3-2 Design and Imp

lementation…..............................442-3-3 Measurement Results......................................462-4 Summary....................................................51Chapter 3 Design of RF CMOS Mixer Circuit for UWB Applications.533-1 Introduction.............................................

..543-2 Principles.................................................553-2-1 Noise Figure Simulated Using P-MOS Switch Circuits.......553-2-2 Noise Figure and Linearity Simulated of A Gilbert Mixerwith Inductive Tuned P-MOS Switch Circuits.....................573-3 Circuit Design .....................

.......................593-4 Measurement Results........................................613-5 Discussion.................................................663-6 Summary....................................................68Chapter 4 Design of RF CMOS VCO circuit for UWB applications...704-1 Introductio

n...............................................704-2 Principles.................................................714-2-1 Switched Inductors Design................................724-2-2 AMOS Varactor Design.....................................744-3 Circuit Design.....................................

........774-4 Measurement Results........................................804-5 Discussion.................................................834-6 Summary....................................................87Chapter 5 Design of RF Transceiver Element for UWB Applications885-1 Introduction..............

.................................885-2 Dumbbell DGS Based Broadband RF Choke for UWB LNA..........905-2-1 Theory and Calculation...................................905-2-2 Design...................................................935-2-3 Results .................................................945-3 S

uspended Substrate Strip-line (SSS) Transition for High QLO Injected Fin-line Mixer.....................................985-3-1 Suspended Substrate Strip-line...........................995-3-2 Fin-line Configuration..................................1025-4 Integrated Millimeter Wave MEMS.............

..............1035-4-1 Fin-line Mixer..........................................1045-4-1-1 Mixer Configuration...................................1045-4-1-2 Mixer Fabrication and Measurement.....................1065-4-2 Millimeter Wave Gun Oscillator..........................1085-4-3 Pin Switch Config

uration................................1095-4-4 Antenna Design..........................................1115-4-5 Integration System......................................1125-4-6 Results.................................................1135-5 Summary...................................................1

14Chapter6 Design of RF Antenna Device for UWB Applications.....1166-1 Introduction..............................................1166-2 60 GHz Compact Slot Antenna Using Substrate IntegratedCircuit Cavity-Backed Waveguides..............................1166-2-1 Design Procedure.......................

.................1186-2-2 Results and Discussions.................................1226-3 MMIC Compatibility Study of SIW H-plane Horn Antenna......1276-3-1 Theory and Design.......................................1286-3-1-1 Overall Design........................................1296-3-1-2 Micro-strip

Transition................................1306-3-1-3 Design for GaAs Process...............................1316-3-2 Experimental Results....................................1326-3-2-1 Micro-strip to SIW Transition.........................1326-3-2-2 100um thick GaAs horn...............................

..1336-3-2-3 300um thick GaAs horn.................................1356-3-3 Summary.................................................137Chapter 7 Conclusions and Future Work.........................1397-1 Conclusions...............................................1397-2 Future Work ...................

...........................143References....................................................145Publication List..............................................157 Figure CaptionsFigure 1-1 Indoor UWB systems spectrum mask.....................4Figure 1-2 Power levels of UWB signal and a typical narrowb

and(NB) signal.....................................................5Figure 1-3 Generic transceiver front-end block diagram,consisted of a receiver and a transmitter.......................6Figure 2-1 Various wideband LNA topologies (a)Shunt feedback(b)Common-gate(c)Cascoded common-source(d)Distribute

d amplifier...13Figure 2-3 Lumped-element equivalent circuits for an incrementallength of transmission line....................................18Figure 2-4 Small-signal model of the MOSFET when the source isconnected to the substrate (body)..............................18Figure 2-5 Small-signal mode

l of the MOSFET after applyingMiller's Theorem...............................................19Figure 2-6 Distributed amplifier transmission line circuits forthe (a) gate line and (b) the drain line.......................19Figure 2-7 Equivalent circuits for single unit cell of (a) gateand (b) drain

line circuits....................................20Figure 2-8 Schematic diagram of the proposed UWB DA............26Figure 2-9 The S21 (power gain) of the DA, CS and overallcircuits.......................................................27Figure 2-10 (a) Measurement setup for input return loss(S11)an

dreverse isolation(S12)(b) measurement setup for power gain(S21)and output return loss (S22)...................................29Figure 2-11 Y-factor method in noise figure measurement setup..30Figure 2-12 General organization of IC-CAP.....................31Figure 2-13 S-parameters measurements ico

......................32Figure 2-14 Gain measurements icon.............................33Figure 2-15 IMD measurements icon..............................33Figure 2-16 Measured and simulated S-parameters of the proposedDA.............................................................34Figure 2-17 Simula

tion and measurement results of noise figure.34Figure 2-18 Photograph of the overall DA.......................35Figure 2-19 Shunt peaking a common source amplifier(a)Simplecommon source amplifier and(b)its equivalent small signal model(c)Common source amplifier with shunt peaking and(d)itsequivalent

small signal model..................................38Figure 2-20 Frequency response of shunt-peaked cases tabulatedin Table 2-2...................................................40Figure 2-21 (a) Traditional cascode amplifier and (b) Cascodeamplifier with current reused............................

......42Figure 2-22 Simulated gain without and with current reused (pre-layout) of UWB PA..............................................43Figure 2-23 Shows traditional current-reused topology with dual-stage current-reused technology both simulation resultscompared....................................

...................44Figure 2-24 Schematic diagram of the proposed UWB PA...........45Figure 2-25 Chip microphotograph of the UWB PA(1.054x0.76 mm2).46Figure 2-26 Measured input return loss (S11)...................47Figure 2-27 Measured output return loss (S22)..................47Figure 2-28 Measure

d power gain (S21)..........................48Figure 2-29 Measured reverses isolation (S12)..................48Figure 2-30 Measured P1dB and IIP3.............................49Figure 2-31 The simulated group delay versus frequencycharacteristics of the 3.1-10.6 GHz CMOS UWB PA................50Figur

e 2-32 Simulated Load-pull contours at 6 GHz (at P1dB =−1.5dBm).......................................................50Figure 3-1 Conventional double-balanced Gilbert mixer in directconversion receiver............................................55Figure 3-2 (a)Gilbert mixer with p-MOS switch circui

ts(b)p-MOSswitch circuits with parasitic capacitances....................56Figure 3-3 (a)Proposed Gilbert mixer with p-MOS switch circuitsresonated by an inductor (b) Equivalent circuits of the single-stage mixers...................................................58Figure 3-4 Down-Conversion Mixers.

.............................59Figure 3-5 The Relationship among C7, R3, and R5...............60Figure 3-6 The Conversion Gain of 0.9~10.6GHz..................61Figure 3-7 RF Input Return Loss................................62Figure 3-8 LO Input Return Loss................................62Figure 3-

9 Shows the measured P1dB at 10.6 GHz.................62Figure 3-10 Shows the measured IIP3 at 10.6 GHz................63Figure 3-11 Noise Figure.......................................63Figure 3-12 Isolation (a) LO to IF and (b) LO to RF............64Figure 3-13 The Relationship of LO Power with Con

version Gain..65Figure 3-14 Chip microphotograph of the UWB Mixer..............65Figure 3-15 Conversion gain for three configurations with inputmatching.......................................................67Figure 3-16 SSB Noise Figure VS. RF &; LO sweep with IF=100MHz..68Figure 4-1 Schematic diag

ram of an adjustable inductor withdifferent kinds of sequential switch operations................73Figure 4-2 Schematic of the AMOS varactor bank.................75Figure 4-3 Circuit schematic of the VCO core ..................76Figure 4-4 Negative resistance -2/gm of the cross coupled PMOS.77Figure

4-5 Adjustable inductor with ground-area variation......77Figure 4-6 VCO using variable inductor.........................78Figure 4-7 Oscillator frequency range versus varactor voltagewith different kinds of switch operations......................79Figure 4-8 Die microphotograph of purposed VCO,wit

h a chip sizeof 0.77x0.62 mm2...............................................80Figure 4-9 The proposed VCO spectrum under(a)switch count = 0,i.e. all-OF state, and (b) switch count = 5, all-ON state......81Figure 4-10 Phase-noise of the purposed VCO performance.......82Figure 4-11 Measured dependenc

e of the phase noise on thecontrol voltage Vc.............................................84Figure 4-12 Measured dependence of the phase noise on the gatevoltage Vg.....................................................85Figure 4-13 Measured dependence of the phase noise on the drainvoltage Vd........

.............................................85Figure 4-14 Phase-noise measurement versus the offsetfrequency......................................................86Figure 5-1 The lumped LC equivalent model of a dumbbell DGSunit cell......................................................91Figure 5-2

Schematic modulated dumbbell pattern................93Figure 5-3 Dumbbell DGS pattern dimension: central element,2r0 = 5.5 mm; adjacent element 2r1=3.5mm;thearm=1.27mmx0.381mmand the spacing a = 8 mm.......................................95Figure 5-4 The fabricated dumbbell DGS choke: (a) back etche

ddumbbell and (b) top 50 Ohms line..............................96Figure 5-5 Simulated (dotted line)and measured(solid line)3.1to 10.6GHz rejection performance of designed dumbbell DGS RFchoke..........................................................97Figure 5-6 Dumbbell DGS RF choke assisted chip p

robing testassembly.......................................................98Figure 5-7 Overlap Section Forming the Series Capacitance.....100Figure 5-8 Structure of SSS band-pass filter..................101Figure 5-9 S21 of SSS band-pass filter........................101Figure 5-10 Antipodal-To-Susp

ended Strip-line Transition......102Figure 5-11 Fin-line taper....................................103Figure 5-12 Fin-line inserted into waveguide..................103Figure 5-13 Fin-line mixer configurations.....................105Figure 5-14 Fin-line Mixers...................................107Figu

re 5-15 S21 of Broadside Coupled Suspended Substrate Stripline Capacitive Coupled Band-pass Filter......................107Figure 5-16 S11 of Broadside Coupled Suspended Substrate Stripline Capacitive Coupled Band-pass Filter......................108Figure 5-17 Fabricated Fin-line PIN switch........

............110Figure 5-18 Fabricated fin-line antenna.......................112Figure 5-19 Received data(bottom)versus transmitted data(top).113Figure 6-1 New SIW slot antenna structure.....................117Figure 6-2 The parameters of designed SIW.....................118Figure 6-3 Cross-sectiona

l view of a BCB SIW layer: (a) Top metallayer (b) Middle strip-line layer and (c) Bottom layer........120Figure 6-4 Designed structures of (a) large area slot (b)central-fed square slot and (c) quarter wavelength from end wallcentral-fed strip-line........................................121Figure 6-

5 (a) to (c) shows the return loss of three designs at60GHz.........................................................123Figure 6-6 shows the (a) E-plane and (b) H-plane radiationpatterns at 60 GHz for large area slot design.................124Figure 6-7 s shows the (a) E-plane and (b) H-plane radiati

onpatterns at 60 GHz for central-fed square slot design.........125Figure 6-8 shows the (a) E-plane and (b) H-plane radiationpatterns at 60 GHz for quarter Wavelength from end wall central-fed strip-line design.........................................126Figure 6-9 The geometry of the SIW horn antenn

a...............130Figure 6-10 Layers of 0.5um GaAs process......................131Figure 6-11 (a) Micro-strip to SIW transition (b) Simulationresult........................................................132Figure 6-12 (a) S-parameter of 100um horn antenna and (b) Sideradiation is small...........

.................................134Figure 6-13 (a) S-parameter of 300um thick horn antenna and (b)Side radiation is improved....................................136Figure 6-14 (a) The chip antenna test set-up using 110 GHznetwork Analyzer and (b) The two port probes are attached tothe antenna micro-

strip transition input each.................137Figure 6-15 Die microphotograph of purposed antenna, with a chipsize of 2x1.8 mm2.............................................138

Table CaptionsTable 2-1 Performance summary of CMOS distributed amplifiers...37Table 2-2 Performance metrics for shunt peaking................40Table 2-3 Comparison of UWB CMOS PA performances.............. 51Table 3-1 Comparison with Previous

work....................... 66Table 4-1 Performance Benchmark............................... 83